The present invention relates to a high-speed transmission system having a low latency for use in an information processing unit, more particularly to improvement in a high-speed transmission system that transmits a serial signal using a plurality of transmission lines in a transmission system that is used for data transmission among a plurality of processors and between the processor and a memory, which requires a highly speedy broadband data transmission.
Conventionally, in such a highly speedy broadband transmission system, generally, transmission was made for parallel data at one period or plural periods among units having a synchronized clock by the use of a plurality of transmission lines in parallel.
Recently, more broadband transmission has been required, the parallel signal number has increased, and reduction of the signal number of LSI (Large Scaled Integration) has been requested as the input/0 output signal number increases drastically.
So as to respond to this request, for example, as disclosed in High Performance Parallel Interface 6400 M bit/s Physical Layer (HIPPI-6400-PH ANSI X3xxx.199x), it was proposed to transmit a serial data signal at high speed and in broadband by the use of a plurality of transmission lines. So as to correctly receive data that operates at high-speed, it is necessary to sample a data signal having a transmission waveform distorted by a transmission medium such as a cable in a narrow determination region of data called an eye. For that end, phase alteration of a build up or a lagging edge that always alters is supervised constantly, and a sampling clock is regulated at the center of alteration points of data by the use of a PLL (Phase Locked Loop) to receive data. But, in a technique disclosed in this prior-art document, as shown in FIG. 14, by adding one bit to data signal 4 bits, a signal is inversed so that ratios of 1 and 0 become equal, whereby continuous occurrence of 0 and 1 is suppressed to cause alteration to occur constantly.
Also, in a single transmission line, like a fiber channel (ANSI XT11 Fiber Channel Physical and Transmission Protocol) so as to reduce the numbers of 1 and 0 (zero) that are continuous, a technique has been employed of converting 8 bits into 10 bits.
For example, in JP-A-340839/1999, was disclosed a parallel-signal serial transmission unit adapted to provide in the send side separator-bit addition/parallel-serial conversion means of adding a synchronizing signal to a parallel data signal to convert it into a serial data signal, and to provide in the receive side separator-bit deletion/serial-parallel conversion means of removing a separator bit from the serial data signal to convert it into a parallel data signal.
Also, in JP-A-216744/2000, was disclosed a data transmission unit that includes synchronizing code addition means of adding a synchronizing code during a specific period of parallel data and parallel/serial conversion means of converting the parallel data to which the synchronizing code was added into serial data.
On the contrary, in the prior art described above, the problem existed: For example, since separator one bit (or two bits) was added to data 4 bits (or 8 bits), 80% of the transmitted data signal was effective data, whereby, so as to transmit the same data volume, it was necessary to use one and a quarter times of circuit volume and transmission line or to raise a transmission speed one and a quarter times.
Also, since time for converting 4-bit (or 8-bit) data into 5-bit (or 10-bit) one so that ratios of 1 and 0 become equal, and time for converting 5-bit (or 10-bit) data into 4-bit one (or 8-bit one) are needed, the problem existed: It required the time (hereinafter, referred to as latency) that the receiver side recovered original data and output it after data that was transmitted was input, and even though transmission was able to be made at a high speed, the time was delayed for being used as data.
But, in the event that 4 bits (or 8 bits) was not converted into 5 bits (or 10 bits), a redundant bit is not added and a data signal takes a free value, whereby means of establishing a specific signal string as a start of data is not able to be employed, and yet it is not be able to be guaranteed that a signal string does alter into 1 and 0, whereby the problem occurs that a sampling clock is not able to be regulated constantly.